1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device incorporating a test mode therein to perform an automatic refresh function.
2. Description of the Related Art
Described below is a general operation of the test mode for measuring a refresh period of DRAM employing the automatic refresh function.
First, an internal address counter counts an oscillation number of an oscillation signal generated by an oscillator which determines the refresh period and outputs the result into an address terminal. Then, judgement is made as to whether the automatic refresh function has been correctly operated by measuring the result output onto the address terminal.
However, there arise the following problems in the DRAM employing the test mode function set forth above when the test circuit operates under a normal operation mode or an automatic refresh operation mode, that is, when a test mode control signal is set to be a Low level.
Namely, when levels of external address signals become below a ground potential level GND due to undershoot or the like, or when the level of the test mode control signal exceeds above the ground potential level GND due to superimposition of noises upon the test mode control signal caused by an operational noise in a circuit, data of the external address signal affects on data output as a refresh address.
As the result, there arise problems that a counter circuit may malfunction or defects may be generated upon continuity of the refresh address.
These kinds of semiconductor memory devices are disclosed, for example, in Japanese Laid-Open Patent Publication 63-148493.